1. Field of the Invention
The present invention relates to a semiconductor memory. More particularly, the present invention relates to a semiconductor memory suitable for DRAM that enables a high-speed operation.
2. Description of the Related Art
FIG. 1 is a block diagram showing the configuration of a conventional technique. A semiconductor memory divided into regions of predetermined units referred to as blocks. Each block is selected by using a block selection signal BS that is an output from a block selection circuit 1.
This semiconductor memory is provided with a memory cell section 5, a redundancy memory cell section 6, a word reset circuit 27, pre-charge circuits 31 and sense amplifiers 32.
The memory cell section 5 makes a predetermined memory cell 11 active based on an main word decoder address signal MWDA and a block selection signal BS. The redundancy memory cell section 6 makes a predetermined redundancy memory cell 21 active based on a redundancy word selection signal RWS and a block selection signal BS. The word reset circuit 27 generates a word reset signal WLR from a block selection signal, and also controls a selected word driver circuit 14 and a redundancy word driver circuit 24. The pre-charge circuit 31 charges bit lines to (xc2xd) VCC. The sense amplifier 32 amplifies a cell data read out to the bit lines.
The memory cell section 5 comprises memory cells 11, a word decoder 13, word driver circuits 14 and a main word decoder 15.
The memory cells 11 are the memory cells for storing data. The word decoder 13 outputs word decode signals (only two signals RA, RA+1 are shown as the representation) based on an address signal from an address buffer 4 and a block selection signal BS. The word driver circuit 14 drives word lines (only two lines WL, WL+1 are shown as the representation) selected by the word decode signals (RA, RA+1) in order to make the predetermined memory cells 11 active. There is a plurality of word driver circuits 14 in the memory cell section 5. The main word decoder 15 generates a main word signal which changes the potential level of the main word lines (WLP to WLP+n) in order to select a predetermined word driver circuit 14 from the plurality of word driver circuits 14.
The memory cell section 6 comprises redundancy memory cells 21, a redundancy word decoder 23, a redundancy word driver circuit 24 and a redundancy main word decoder 25. The redundancy memory cells 21 are the memory cells for storing data. The redundancy word decoder 23 outputs redundancy word decode signals (only two signals RRA, RRA+1 are shown as the representation) based on a block selection signal BS. The redundancy word driver circuit 24 drives redundancy word lines (only two lines RWL, RWL+1 are shown as the representation) selected by the redundancy word decode signals (RRA, RRA+1) in order to make the predetermined redundancy memory cell 21 active. The redundancy main word decoder 25 generates a redundancy main word signal, which changes the potential level of the redundancy main word line RWLP in order to select a redundancy word driver circuit 24.
The memory cell 11 and the redundancy memory cell 21 comprise n-MOSFETs and capacitance elements, respectively as shown in FIG. 4. The standard potential is (xc2xd) VCC.
FIG. 2 shows the conventional reset circuit. The word reset circuit 27 is provided with a delay circuit 27a, a NAND 27b, inverter 27c and inverter 27d.
The word driver circuit 14 is controlled based on a voltage of the main word line WLP. It comprises a transistors T1 to T8.
The transistor T1 has a source connected to the word decoder 13, a gate connected to the drain of the transistor T2, and a drain connected to one of word lines WL. The transistor T1 makes one of word lines WL active by using the word decode signal RA. The transistor T2 has a source connected to the main word decoder 15, a gate connected to a high potential level power supply VCC, and a drain connected to the gate of the transistor T1. The transistor T3 has a source connected to a low potential level power supply GND, a gate connected to a pull-down signal line 14L for the pull-down signal 14a, and a drain connected to the word line WL. The transistor T102 makes the active word line WL inactive by using a pull-down signal 14a. The transistor T4 has a source connected to a pull-down signal line 14L for the pull-down signal 14a, a gate connected to an output of the word reset circuit 27, and a drain connected to a high potential level power supply VCC. The transistor T5 has a source connected to a low potential level power supply GND, a gate connected to the main word line WLP, and a drain connected to the pull-down signal line 14L.
Since the transistors T6 to T8 correspond to the transistors T1 to T3 respectively, the explanation for the transistors T6 to T8 are omitted.
The redundancy word driver circuit 24 is configured similarly to that of the word driver circuit 14. The redundancy word driver circuit 24 is designed so as to be selected by using the word reset signal WLR of the word reset circuit 27.
In the conventional operation of activating a word line WL, the operation timing having the above-mentioned configuration will be described below with reference to FIG. 5.
In the conventional circuit, the redundancy main word line RWLP is not operated in a case of a selection of the memory cell 11. It is operated only when the redundancy cell 21 is selected. Thus, the input of the word reset circuit 27 uses the block selection signal BS.
It is necessary to prevent an penetration current (excessive current) from flowing through the transistors T4 and T5, when the transistors T4 and T5 of FIG. 2 are turned on at the same time. It occurs at the timing that the word reset signal WLR is activated at the same timing of pulling up the potential level of main word line WLP.
An general decoder circuit is constituted by several stages of logical gates, as illustrated by an example shown in FIG. 3. Typically, as the number of addresses is increased, the number of gate stages is increased, and a gate delay is also added.
The word reset circuit 27 has a delay circuit, correspondingly to the configuration of the main word decoder circuit. The delay circuit is adjusted so that the transistors T4 and T5 of FIG. 2 are not turned on at the same time.
As for the operational timing to select a predetermined word driver circuit 14 from the plurality of word driver circuits 14 in FIG. 5, firstly, the block selection signal BS becomes the high potential level. At a time t1, the transistor T4 is on, and the transistor T5 is off. After the time t1, the word reset signal WLR becomes the low potential level. At a time t3, both the transistors T4 and T5 are off. After the time t3, the main word line WLP becomes the high potential level. At and after a time t5, the transistor T4 is off, and the transistor T5 is on. After the time t5, a contact R becomes the low potential level.
Also, to deselect a predetermined word driver circuit 14, firstly, the block selection signal BS becomes the low potential level. Then, the main word line WLP becomes the low potential level. At a time t4, both the transistors T4 and T5 are off. After the time t4, the word reset signal WLR becomes the high potential level. At the time t6, the transistor T4 is on, and the transistor T5 is off. After a time t6, the contact R becomes the high potential level.
By considering the yield of the memory cell array, especially by considering the using redundancy memory cells 21, this is designed so as to give a margin to the time t4 by using the delay circuit 27a. 
In this way, the above-mentioned circuits can attain the expected operation by using the delay circuit 27a. However, the rising timing of the word reset signal WLR is delayed in order to reserve the operational margin. Thus, it is difficult to make the speed of the operation faster.
In conjunction with the above description, the semiconductor memories are disclosed in Japanese Patent Publication and Japanese Laid Open Patent Application.
Japanese Patent Publication No. 2842181 discloses the following semiconductor memory. The semiconductor memory is provided with memory cell arrays, a plurality of word line drivers, and a decoder. The memory cell arrays are divided into a plurality of groups. The plurality of word line drivers is mounted correspondingly to the groups in order to drive respective word lines mounted in word directions of those memory cell arrays. The decoder for decoding an outer address, and thereby generating a word line selection signal, and then controlling the plurality of word line drivers selectively and actively. So, this also contains a generator for generating a word line reset signal which becomes active at a reset time prior to the execution of an operation for selecting the word line, and then resetting the word line. All the word lines are set parallel to each other. The word line reset signal common to the respective word line drivers is set vertical to the word line.
Japanese Laid Open Patent Application (JP-A-Heisei, 8-87884) discloses the following semiconductor memory. The semiconductor memory is provided with word lines, line decoders, word drivers, and word reset transistors. The word lines are to make memory cells arranged in a form of matrix active. The line decoders are for controlling voltages of the respective word lines. First and second transistors that are connected in series between the word line and a ground constitute the word reset transistor. The first transistor is controlled by an output signal from the line decoder. In the second transistor, its gate voltage is applied while a power supply besides the boost power supply and a low voltage power supply whose potential level is lower than the power supply besides the boost power supply and the boost power supply are temporally switched.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-144458) discloses the following semiconductor integrated circuit device. The semiconductor integrated circuit device is provided with a main word driver, a main word driver unit, and a negative word line manner of a level conversion sub-word driver. The main word driver is for outputting a drive signal to drive a main word line based on a pre-decode signal, and a selection signal corresponding to the driven main word line. The main word driver unit is composed of a first booster for boosting the selection signal of the main word driver to a first voltage and a second booster for boosting the drive signal of the main word driver to the first voltage. The negative word line manner of the level conversion sub-word driver is for: sending the first voltage of the first booster to a sub-word line when it is selected by the selection signal and the drive signal of the main word driver; converting standard potential into a first negative voltage and sending it to the sub-word line when it is not selected.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-203858) discloses the following word line driver and semiconductor memory. The word line driver and the semiconductor memory are provided with a first insulation gate type of an electric field transistor and a second insulation gate type of an electric field transistor. The first insulation gate type of an electric field transistor is connected between a first node and a word line and sends a voltage on the first node onto the word line when it is turned on. The second insulation gate type of an electric field transistor is connected between a second node and the word line and sends a voltage on the second node onto the word line when it is turned on. Moreover, this contains a unit for sending a predetermined voltage to the second node, and further generating a signal to control an operation for turning on and off the first and second insulation gate electric field transistors, based on an address signal. In the unit, a resistance between a source and a drain, when the second insulation gate type of the electric field transistor is turned off, is smaller than a resistance between a source and a drain, when the first insulation gate type of the electric field transistor is turned off.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-288587) discloses the following semiconductor integrated circuit device. The semiconductor integrated circuit device is a non-selection negative word line manner of a semiconductor integrated circuit device for converting the low potential level on a word line amplification into a negative voltage lower than a standard voltage. This is characterized in that it contains a mat controller for controlling a reset timing of the word line in a memory mat configured by virtually dividing a memory cell array, and then delaying the reset timing of the word line when the plurality of word lines are selected.
Therefore, an object of the present invention is to provide a semiconductor memory that enables a high-speed operation.
Another object of the present invention is to provide a semiconductor memory that is not necessary to consider the variation of memory cells.
Still another object of the present invention is to provide a semiconductor memory that does not have the delay circuits which is used for word reset operation.
Yet still another object of the present invention is to provide a semiconductor memory that to enable reduce the current used in the memory, and to decrease an electric power consumption.
It is also an object to provide a semiconductor memory manufactured at a low cost by reducing the elements in the semiconductor memory.
In order to achieve an aspect of the present invention, the present invention provides a semiconductor memory including a block selection circuit, a redundancy main word decoder, a word reset circuit and a word driver circuit. The block selection circuit outputs a block selection signal based on an address signal. The redundancy main word decoder generates a redundancy main word signal in response to the block selection signal. The word reset circuit outputs a word reset signal in response to the redundancy main word signal. The word driver circuit which drives one of word lines in response to the word reset signal, a main word signal indicating selection of the word driver circuit, and a word decode signal indicating selection of the one of word lines.
In the semiconductor memory, the redundancy main word decoder generates the redundancy main word signal in response to a redundancy main word control signal indicating a request for generating the redundancy main word signal, in addition to the block selection signal.
The semiconductor memory of the present invention further includes a main word decoder and a word decoder. The main word decoder generates the main word signal based on the address signal and the block selection signal. The word decoder outputs the word decode signal based on the address signal and the block selection signal.
In the semiconductor memory, the word reset circuit is composed of one stage of an inverter or odd number of inverters.
In the semiconductor memory, the word driver circuit includes a first transistor to an eighth transistor. The first transistor has a source connected to the word decoder, a gate connected to a drain of a second transistor, and a drain connected to one of the word lines. The second transistor has a source connected to the main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the first transistor. The third transistor has a source connected to a low potential level power supply, a gate connected to a first pull-down signal line, and a drain connected to the one of the word lines. The fourth transistor has a source connected to the first pull-down signal line, a gate connected to the word reset circuit, and a drain connected to a high potential level power supply. The fifth transistor has a source connected to a low potential level power supply, a gate connected to the main word decoder, and a drain connected to the first pull-down signal line. The sixth transistor has a source connected to the word decoder, a gate connected to a drain of the seventh transistor, and a drain connected to another one of the word lines. The seventh transistor has a source connected to the main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the sixth transistor. The eighth transistor has a source connected to a low potential level power supply, a gate connected to the first pull-down signal line, and a drain connected to the another one of the word lines.
In the semiconductor memory, a transistor size of the fifth transistor is smaller than that of the fourth transistor.
In the semiconductor memory, a carrier mobility of the fifth transistor is smaller than that of the fourth transistor.
In the semiconductor memory, the main word signal and the redundancy main word signal become the high potential level or the low potential level at the substantially same time.
The semiconductor memory further includes a redundancy word decoder and a redundancy word driver circuit. The redundancy word decoder outputs a redundancy word decode signal based on the block selection signal and a redundancy word selection signal indicating selection of the redundancy word decoder. The redundancy word driver circuit drives one of redundancy word lines in response to the word reset signal, the redundancy main word signal and the redundancy word decode signal.
In the semiconductor memory, the word reset circuit includes one stage of an inverter or odd number of inverters.
In the semiconductor memory, the redundancy word driver circuit includes a ninth transistor to an eighth transistor. The ninth transistor has a source connected to the redundancy word decoder, a gate connected to a drain of a tenth transistor, and a drain connected to one of the redundancy word lines. The tenth transistor has a source connected to the redundancy main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the ninth transistor. The eleventh transistor has a source connected to a low potential level power supply, a gate connected to a second pull-down signal line, and a drain connected to the one of the redundancy word lines. The twelfth transistor has a source connected to the second pull-down signal line, a gate connected to the word reset circuit, and a drain connected to a high potential level power supply. The thirteenth transistor has a source connected to a low potential level power supply, a gate connected to the redundancy main word decoder, and a drain connected to the second pull-down signal line. The fourteenth transistor has a source connected to the redundancy word decoder, a gate connected to a drain of a fifteenth transistor, and a drain connected to another one of the redundancy word lines. The fifteenth transistor has a source connected to the redundancy main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the fourteenth transistor. The sixteenth transistor has a source connected to a low potential level power supply, a gate connected to the second pull-down signal line, and a drain connected to the another one of the redundancy word lines.
In the semiconductor memory, a transistor size of the thirteenth transistor is smaller than that of the twelfth transistor.
In the semiconductor memory, the main word signal and the redundancy main word signal become the high potential level or the low potential level at the substantially same time.
In order to achieve another aspect of the present invention, the present invention provides a semiconductor memory including a block selection circuit,a main word decoder, a word reset circuit, a word driver circuit and a word driver circuit. The block selection circuit outputs a block selection signal based on an address signal. The main word decoder generates a main word signal based on the address signal and the block selection signal. The word reset circuit outputs a word reset signal in response to the main word signal. The word driver circuit drives one of word lines in response to the word reset signal, the main word signal and a word decode signal.
The semiconductor memory of the present invention further includes a word decoder outputting the word decode signal based on the address signal and the block selection signal.
In the semiconductor memory, the word reset circuit includes one stage of an inverter or odd number of inverters.
In the semiconductor memory, the word driver circuit includes a first transistor to eighth transistor. The first transistor has a source connected to the word decoder, a gate connected to a drain of a second transistor, and a drain connected to one of the word lines. The second transistor has a source connected to the main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the first transistor. The third transistor has a source connected to a low potential level power supply, a gate connected to a first pull-down signal line, and a drain connected to the one of the word lines. The fourth transistor has a source connected to the first pull-down signal line, a gate connected to the word reset circuit, and a drain connected to a high potential level power supply. The fifth transistor has a source connected to a low potential level power supply, a gate connected to the main word decoder, and a drain connected to the first pull-down signal line. The sixth transistor has a source connected to the word decoder, a gate connected to a drain of a seventh transistor, and a drain connected to another one of the word lines. The seventh transistor has a source connected to the main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the sixth transistor. The eighth transistor having a source connected to a low potential level power supply, a gate connected to the first pull-down signal line, and a drain connected to the another one of the word lines.
In the semiconductor memory, a transistor size of the fifth transistor is smaller than that of the fourth transistor.
The semiconductor memory of the present invention, further includes a redundancy main word decoder, a redundancy word decoder, a redundancy word reset circuit, a redundancy word driver circuit. The redundancy main word decoder generates a redundancy main word signal based on the block selection signal and a redundancy main word control signal indicating a request for generating the redundancy main word signal. The redundancy word decoder outputs a redundancy word decode signal based on the block selection signal and a redundancy word selection signal. The redundancy word reset circuit outputs a redundancy word reset signal in response to the redundancy main word signal. The redundancy word driver circuit drives one of redundancy word lines in response to the redundancy word reset signal, the redundancy main word signal and the redundancy word decode signal.
In the semiconductor memory, the redundancy word reset circuit includes one stage of an inverter or odd number of inverters.
In the semiconductor memory, the redundancy word driver circuit includes a ninth transistor to a sixteenth transistor. The first transistor has a source connected to the redundancy word decoder, a gate connected to a drain of a tenth transistor, and a drain connected to one of the redundancy word lines. The tenth transistor has a source connected to the redundancy main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the ninth transistor. The eleventh transistor has a source connected to a low potential level power supply, a gate connected to a second pull-down signal line, and a drain connected to the one of the redundancy word lines. The twelfth transistor has a source connected to the second pull-down signal line, a gate connected to the word redundancy reset circuit, and a drain connected to a high potential level power supply. The thirteenth transistor has a source connected to a low potential level power supply, a gate connected to the redundancy main word decoder, and a drain connected to the second pull-down signal line. The fourteenth transistor has a source connected to the redundancy word decoder, a gate connected to a drain of a fifteenth transistor, and a drain connected to another one of the redundancy word lines. The fifteenth transistor has a source connected to the redundancy main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the fourteenth transistor. The sixteenth transistor has a source connected to a low potential level power supply, a gate connected to the second pull-down signal line, and a drain connected to the another one of the redundancy word lines.
In the semiconductor memory, a transistor size of the thirteenth transistor is smaller than that of the twelfth transistor.
In the semiconductor memory, the word driver circuit includes a seventeenth transistor to twenty-sixth transistor. The seventeenth transistor has a source connected to the word decoder, a gate connected to a drain of a eighteenth transistor, and a drain connected to one of the word lines. The eighteenth transistor has a source connected to the main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the seventeenth transistor. The nineteenth transistor has a source connected to a low potential level power supply, a gate connected to a source of a twentieth transistor, and a drain connected to the one of the word lines. The twentieth transistor has the source connected to the gate of the nineteenth transistor, a gate connected to the word reset circuit, and a drain connected to a high potential level power supply. The twenty-first transistor has a source connected to a low potential level power supply, a gate connected to the main word decoder, and a drain connected to the source of the twentieth transistor. The twenty-second transistor has a source connected to the word decoder, a gate connected to a drain of a twenty-third transistor, and a drain connected to another one of the word lines. The twenty-third transistor has a source connected to the main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the twenty-second transistor. The twenty-fourth transistor has a source connected to a low potential level power supply, a gate connected to a source of a twenty-fifth transistor, and a drain connected to the another one of the word lines. The twenty-fifth transistor has the source connected to the gate of the twenty-fourth transistor, a gate connected to the word reset circuit, and a drain connected to a high potential level power supply. The twenty-sixth transistor has a source connected to a low potential level power supply, a gate connected to the main word decoder, and a drain connected to the source of the twenty-fifth transistor.
In the semiconductor memory, the redundancy word driver circuit includes a twenty-seventh transistor to thirty-sixth transistor. The twenty-seventh transistor has a source connected to the redundancy word decoder, a gate connected to a drain of a twenty-eighth transistor, and a drain connected to one of the redundancy word lines. The twenty-eighth transistor has a source connected to the redundancy main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the twenty-seventh transistor. The twenty-ninth transistor has a source connected to a low potential level power supply, a gate connected to a source of a thirtieth transistor, and a drain connected to the one of the redundancy word lines. The thirtieth transistor has a source connected to the gate of the twenty-ninth transistor, a gate connected to the word reset circuit, and a drain connected to a high potential level power supply. The thirty-first transistor has a source connected to a low potential level power supply, a gate connected to the redundancy main word decoder, and a drain connected to the source of thirtieth transistor. The thirty-second transistor has a source connected to the redundancy word decoder, a gate-connected to a drain of a thirty-third transistor, and a drain connected to another one of the redundancy word lines. The thirty-third transistor has a source connected to the redundancy main word decoder, a gate connected to a high potential level power supply, and the drain connected to the gate of the thirty-second transistor. The thirty-fourth transistor has a source connected to a low potential level power supply, a gate connected to a source of a thirty-fifth transistor, and a drain connected to the another one of the redundancy word lines. The thirty-fifth transistor has a source connected to the gate of the thirty-fourth transistor, a gate connected to the word reset circuit, and a drain connected to a high potential level power supply. The thirty-sixth transistor having a source connected to a low potential level power supply, a gate connected to the redundancy main word decoder, and a drain connected to the source of thirty-fifth transistor.
In order to achieve still another aspect of the present invention, the present invention provides a method of driving a word line, including: (a) activating a block selection signal based on an address signal; (b) activating a redundancy main word signal in response to the block selection signal; (c) activating a word reset signal in response to the redundancy main word signal; and (d) activating a word line in response to a word reset signal, a main word signal, and a word decode signal.
In the method of driving a word line, the (b) activating the redundancy main word signal step includes (e) activating the redundancy main word signal in response to a redundancy main word control signal indicating a request for generating the redundancy main word signal, in addition to the block selection signal.
In the method of driving a word line, the (d) activating the word line step includes (f) activating the main word signal based on the address signal and the block selection signal; and (g) activating the word decode signal based on the address signal and the block selection signal.
The method of driving a word line further includes (h) inactivating the word line in response to the word decode signal; (i) inactivating the block selection signal based on the address signal; (j) inactivating a redundancy main word signal based on the block selection signal and redundancy main word control signal; and (k) inactivating a word reset signal in response to the redundancy main word signal.